Verification of Bounded Delay Asynchronous Circuits with Timed Traces
نویسندگان
چکیده
In this paper, we extend the verification method based on trace theory by Dill et al. such that it can handle bounded delay asynchronous circuits and check certain liveness properties as well as safety properties. We use time Petri nets to model both bounded delay circuits and timed properties to be verified. Some experimental results are also shown to demonstrate the proposed method.
منابع مشابه
Veri cation of Bounded Delay Asynchronous Circuits with Timed Traces
In this paper, we extend the veriication method based on the failure semantics of process algebra and the resulting trace theory by Dill et al. for bounded delay asynchronous circuits. We deene a timed conformance relation between trace structures which allows to express both safety and responsiveness properties. In our approach, bounded delay circuits as well as their real-time properties are ...
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